1. Field of the Invention
The present invention relates to packaging processes, and more particularly, to an electronic package and a fabrication method thereof for saving the fabrication cost.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Accordingly, there have been developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip modules (MCM), and 3D IC chip stacking technologies.
FIGS. 1A to 1F are schematic cross-sectional views showing a method for fabricating a 3D chip stacking-type electronic package 1 according to the prior art.
Referring to FIG. 1A, a silicon substrate 10 having a chip mounting side 10a and an opposite external connection side 10b is provided, and a plurality of via holes 100 are formed on the chip mounting side 10a of the silicon substrate 10.
Referring to FIG. 1B, an insulating material 102 and a conductive material such as copper are filled in the via holes 100 to form a plurality of through silicon vias (TSVs) 101. Then an RDL (Redistribution Layer) structure is formed on the chip mounting side 10a of the silicon substrate 10 and electrically connected to the TSVs 101.
In particular, to form the RDL structure, a dielectric layer 11 is first formed on the chip mounting side 10a of the silicon substrate 10. Then, a circuit layer 12 is formed on the dielectric layer 11 and has a plurality of conductive vias 120 formed in the dielectric layer 11 and electrically connected to the TSVs 101. Thereafter, a solder mask layer 13 is formed on the dielectric layer 11 and the circuit layer 12, exposing portions of the circuit layer 12.
Further, a plurality of solder bumps 14 can be formed on the exposed portions of the circuit layer 12.
Referring to FIG. 1C, mechanical grinding and CMP (chemical mechanical polishing) processes are performed on the external connection side 10b of the silicon substrate 10 to remove a portion of the silicon substrate 10, thereby forming an external connection side 10b′ exposing one end surfaces of the TSVs 101.
Referring to FIG. 1D, another solder mask layer 15 is formed on the external connection side 10b′ of the silicon substrate 10, exposing the end surfaces of the TSVs 101. Then, a plurality of conductive elements 16 are formed on the end surfaces of the TSVs 101 so as to be electrically connected to the TSVs 101. The conductive elements 16 can include a solder material or can be copper bumps. Further, the conductive elements 16 can selectively include a UBM (Under Bump Metallurgy) layer 160.
Referring to FIG. 1E, a singulation process is performed along cutting paths S of FIG. 1D to obtain a plurality of silicon interposers 1a. Then, such a silicon interposer 1a is disposed on a packaging substrate 19 through the conductive elements 16. In particular, the packaging substrate 19 has a plurality of conductive pads 190 electrically connected to the TSVs 101 through the conductive elements 16, and the conductive pads 190 have a large pitch therebetween. Subsequently, an underfill 191 is formed between the silicon interposer 1a and the packaging substrate 19 to encapsulate the conductive elements 16.
Referring to FIG. 1F, a plurality of semiconductor chips 17 are disposed on the solder bumps 14 so as to be electrically connected to the circuit layer 12. In particular, the semiconductor chips 17 are flip-chip bonded to the solder bumps 14, and an underfill 171 is formed between the semiconductor chips 17 and the silicon interposer 1a to encapsulate the solder bumps 14. The electronic elements 17 have a plurality of electrode pads having a small pitch therebetween.
Then, an encapsulant 18 is formed on the packaging substrate 19 to encapsulate the semiconductor chips 17 and the silicon interposer 1a. 
Finally, a plurality of solder balls 192 are formed on a lower side of the packaging substrate 19 for mounting an electronic device, for example, a circuit board (not shown). As such, an electronic package 1 is obtained.
In the electronic package 1, the silicon interposer 1a serves as a signal transmission medium between the semiconductor chips 17 and the packaging substrate 19. To achieve a suitable silicon interposer 1a, the TSVs 101 must be controlled to have a certain depth to width ratio (100 um/10 um), thus consuming a large amount of time and chemical agent and incurring a high fabrication cost.
Further, during the CMP process, copper ions of the TSVs 101 can diffuse into the silicon substrate 10 and cause bridging or leakage problems between the TSVs 101.
Furthermore, the silicon interposer 1a leads to an increase in thickness of the electronic package 1 and hinders thinning of the electronic package 1.
Therefore, how to overcome the above-described drawbacks has become critical.